Analog-Baseband Architectures And Circuits For Multistandard by Pui-In Mak, Ben U Seng Pan, Rui Paulo Martins

By Pui-In Mak, Ben U Seng Pan, Rui Paulo Martins

With the previous few decade efforts on lithography and integrated-circuit (IC) applied sciences, very inexpensive microsystems were effectively built for lots of assorted purposes. the fad in instant communications is towards making a networkubiquitous period within the years yet to come. Many unheard of possibilities and demanding situations, reminiscent of layout for multi-standardability and low-voltage (LV) compliance, are quickly changing into the mainstream instructions in wireless-IC learn and improvement, on condition that the previous can provide the simplest connectivity between assorted networks, whereas the latter can facilitate the expertise migration into the sub-1-V nanoscale regimes for extra fee and tool aid.

Analog-Baseband Architecturees and Circuits presents architectural and circuit concepts for instant transceivers to accomplish multistandard and low-voltage compliance. the 1st a part of the booklet experiences the actual layer requirements of contemporary instant conversation criteria, offers the basic tradeoffs curious about transceiver structure choice, and offers case stories of the state of the art multistandard transceivers, the place the most important strategies bolstered are highlighted and mentioned. A statistical precis (with a hundred+ references pointed out) of so much used transmitter and receiver architectures for contemporary communique criteria is supplied. all of the references are citied from the best boards, i.e., ISSCC, CICC, VLSI and ESSCIRC, from 1997 to 2005.

The moment half makes a speciality of the architectural layout of multistandard transceivers. A coarse-RF fine-IF (two-step) channelselection strategy is disclosed. It, during the reconfiguration of receiver and transmitter analog basebands, permits not just a leisure of the RF frequency synthesizer’s and native oscillator’s layout necessities, but in addition an effective multistandard compliance via synthesizing the low-IF and zero-IF within the receiver; and the direct-up and two-step-up within the transmitter. the main is verified in few layout examples. one in every of them is a system-in-a-package (SiP) receiver analog baseband for IEEE 802.11a/b/g WLAN. It not just has the two-step channel choice embedded, but additionally incorporates a flexible-IF topology, a different 3D-stack floorplan, and a specific layout technique for prime testability and routability.

The 3rd half bargains with the circuit layout. as well as the methodical description of many LV circuit innovations, three tailormade LV-robust practical blocks are provided. They contain: 1) a double-quadrature-downconversion clear out (DQDF) – it realizes simultaneously clock-rate-defined IF reception, I/Q demodulation, IF channel choice and baseband filtering. 2) A switched-current-resistor (SCR) programmable-gain amplifier (PGA) – it bargains a transient-free constant-bandwidth achieve adjustment. three) An inside-OpAmp dc-offset canceler – it saves the silicon quarter required for figuring out a wide time consistent on chip whereas maximizing its highpass-pole switchability for quick dc-offset transient.

The final half offers experimental result of the three tailored development blocks and a fully-integrated analog-baseband IC fabricated in a standard-VTH CMOS approach. formerly untold on-/off-chip co-setup for either full-chip and development blocks measurements are defined. not just the development blocks have effectively prolonged the state of the art boundary when it comes to sign bandwidth and provide voltage, the analog-baseband IC has been up to now the lowest-voltage-reported answer for IEEE 802.11a/b/g WLAN receivers.

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Such a filter performs not only channel selection, but also relaxes the I/Q-matching requirement from the PGAs and A/Ds. Figure 2-4. Low-IF RX implemented in different ways: (a) case-I (b) II (c) III and (d) IV Case-III is another combination employing a complex filter together with an analog IF-to-BB downconverter for doubling the image rejection. With such a structure, the I/Q matching required from the following PGA and A/D are very relaxed. The bandwidth of the PGAs and the conversion rate of the A/Ds are reduced to their minimum like zero-IF.

With the abbreviation of each type RX and TX architecture listed in Table 2-7, the distributions of each type of RX and TX employed in the modern wireless communication systems are plotted in Figure 2-8 and 2-9, respectively. The publications are listed in the References Part II. They are classified by their applications and corresponding architectures. 22 Analog-Baseband Architectures and Circuits Table 2-7. Abbreviations of TX and RX architectures SH: Superheterodyne PLL: Phased-locked Loop Modulation POLAR: Polar Modulation DUAL: Dual-Conversion WEAVER: Weaver LIF: Low-IF ZIF: Zero-IF DU: Direct-up 2SU: Two-Step-Up HIF: High IF Figure 2-8.

182–183, Feb. 2004. 38] H. 18μm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 96–97, Feb. 2005. 39] P. 11b Wireless LAN,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 204–205, Feb. 2001. 40] G. 11b Wireless LAN Application,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 358–359, Feb. 2003. 41] W. 11b Wireless LANs,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp.

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