Microwaves

60-GHz CMOS Phase-Locked Loops by Hammad M. Cheema, Reza Mahmoudi, Arthur H.M. van Roermund

By Hammad M. Cheema, Reza Mahmoudi, Arthur H.M. van Roermund

The promising excessive information cost instant purposes at millimeter wave frequencies typically and 60 GHz particularly have received a lot cognizance in recent times. although, demanding situations regarding circuit, structure and measurements in the course of mm-wave CMOS IC layout need to be triumph over sooner than they could develop into conceivable for mass market.

60-GHz CMOS Phase-Locked Loops concentrating on phase-locked loops for 60 GHz instant transceivers elaborates those demanding situations and proposes ideas for them. The method point layout to circuit point implementation of the full PLL, in addition to separate implementations of person parts corresponding to voltage managed oscillators, injection locked frequency dividers and their combos, are integrated. in addition, to meet a few transceiver topologies concurrently, flexibility is brought within the PLL structure through the use of new dual-mode ILFDs and switchable VCOs, whereas reusing the low frequency parts on the similar time.

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Therefore, the calibration data for a particular ISS is specified only for a specific probe spacing and ISS combination. The probe type, for instance GSG or GSGSG also need unique calibration data and ISS for the latter should not be used for the former to maintain calibration accuracy. 52 3 Layout and Measurements at mm-Wave Frequencies 40 GHz –15 dBm After de-embedding G G Probe G G S DUT S Probe After calibration Fig. 15 Illustration of calibration and de-embedding procedures for accurate measurements l l l l The importance of the probe position on the bond-pads (as mentioned in the previous section) is more evident during a calibration procedure for mm-wave measurements.

This means that firstly, RF interconnects carrying the high frequency signals should be as short as possible, secondly, the long interconnects should be realized as transmission lines (T-lines) having a controlled impedance and termination, and thirdly, the interconnects in the vicinity of above dimensions have to be treated in a distributed fashion involving meticulous calculations or electromagnetic (EM) simulations. The guideline of 146 mm only provides the first bound. However, in reality the cut-off is application and frequency dependent.

However, this is not the case as the operation frequency moves into the mm-wave regime. Consequently, realizing high quality-factor (Q) inductors, which is already a challenge at frequencies in excess of 10 GHz, becomes even more demanding due to the substrate induced losses. A number of solutions can be adopted to address this loss mechanism: l l High resistivity substrates with $10 kΩ-cm can be used to decrease the induced currents. Un-doped silicon or insulators such as sapphire have been used in Silicon-on-Insulator (SOI) technologies to achieve high resistivity.

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